If an instruction accesses a register that a preceding instruction overwrites in a subsequent cycle, data hazards exist. Pipelining will yield inaccurate results unless we reduce data risks.
In this article, we will dive deeper into the concept of Data Hazards according to the GATE Syllabus for (Computer Science Engineering) CSE. Read ahead to learn more.
Table of Contents
What are Data Hazards?
When the execution of an instruction is dependent on the results of a prior instruction that’s still being processed in a pipeline, data hazards occur. Consider the following scenario.
The result of the ADD instruction is written into the register X3 at t5 in the example above. If bubbles aren’t used to postpone the following SUB instruction, all the three operations will use data from X3, that is earlier in the ADD process. The program has gone haywire!
Solutions to Data Hazard
The following are some of the probable solutions:
Solution 1:
At the IF stage of the SUB instruction, add three bubbles. This will make it easier for SUB – ID to work at t6. As a result, all subsequent instructions in the pipe are similarly delayed.
Solution 2:
Forwarding of Data – Data forwarding is the process of sending a result straight to that functional unit which needs it: a result is transferred from one unit’s output to another’s input. The goal is to have the solution ready for the next instruction as soon as possible.
In this scenario, the ADD result can be found at the ALU output in ADD –IE, that is the t3 end. In case the control unit can control and forward this to the SUB-IE stage at t4 just before writing to the output register X3, the pipeline will proceed without halting. This necessitates additional processing to detect and respond to this data hazard. It’s worth noting that, though Operand Fetch normally occurs in the ID stage, it’s only utilised in the IE stage. As a result, the IE stage receives forwarding as an input. OR and AND instructions can also be used to forward data in a similar way.
Solution 3:
When generating executable code, the compiler can recognise data dependencies and reorganise (resequence) the instructions appropriately. This will make the device easier to use.
Solution 4:
If the reordering described above is not possible, the compiler can detect and insert a no operation (or NOP) instruction(s). NOP refers to a software-generated dummy instruction equivalent bubble.
During the code optimization stage of the compilation process, the compiler examines data dependencies.
Classification of Data Hazards
Data hazards are divided into three types according to the order in which READ or WRITE operations are performed on the register:
Flow/True Data Dependency [RAW (or Read after Write)]
This is when one instruction makes use of data from a previous instruction.
Example,
ADD X0, X1, X2
SUB X4, X3, X0
Anti-Data Dependency [WAR (or Write after Read)]
When the second instruction is written to a register before the first instruction is read, this is known as a race condition. In case of a simple structure of a pipeline, this is uncommon. WAR, on the other hand, can occur in some machines having complex and specific instructions.
Example,
ADD X2, X1, X0
SUB X0, X3, X4
Output data dependency [WAW (or Write after Write)]
This is a situation where two simultaneous instructions must write the same register in the same sequence they were issued.
Example,
ADD X0, X1, X2
SUB X0, X4, X5
Only when instructions are parallelly executed or out of sequence may WAW and WAR dangers exist. These arise because the compiler has allotted the very same register numbers, which may have been avoided. This problem can be solved by the compiler renaming one of these registers or waiting for the updating of a given register until the proper value has been generated. Modern CPUs include not only parallel execution with various ALUs, they also include out-of-order instruction issuing and execution, as well as many pipeline stages.
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Also Explore,
- Types of Instructions in Computer Architecture
- Arithmetic Pipeline in Computer Architecture
- Control Hazards in Computer Architecture
- Instruction Pipeline in Computer Architecture
- Memory Organization in Computer Architecture
- Pipeline Hazards in Computer Architecture
- Pipelining in Computer Architecture
- Structural Hazards in Computer Architecture
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