In the indexed addressing mode, the content of a given index register gets added to an instruction’s address part so as to obtain the effective address. Here, the index register refers to a special CPU register that consists of an index value. An instruction’s address field defines the beginning address of any data array present in memory.
In this article, we will take a look at the Index Addressing Mode according to the GATE Syllabus for CSE (Computer Science Engineering). Read ahead to learn more.
Table of Contents
Index Addressing Mode
The index addressing mode is pretty helpful whenever the instructions in a program access an array or large ranges of memory addresses. The effective address, in such a mode, is generated when we add a constant to the content of the register. The register content does not ever change.
Here is a symbolic representation of the index addressing mode. It can be denoted as follows:
X(R)
The effective address here is denoted as follows:
EA = X + (R)
Consider the instruction given below, for instance:
Load R2, A
Load R3, (R2)
Load R4, 4(R2)
Load R5, 8(R2)
Load R6, 12(R2)
The instructions given above will load the R3, R4, R5, R6 registers, along with the contents that are present at the successive memory addresses correspondingly from the memory location A.
Advantage
Using the index addressing mode, we get flexibility for specifying several locations of the memory.
Disadvantage
It is very complex to implement the index addressing mode.
Keep learning and stay tuned to get the latest updates on GATE Exam along with GATE Eligibility Criteria, GATE 2023, GATE Admit Card, GATE Syllabus, GATE Previous Year Question Paper, and more.
Also Explore,
Comments