An instruction pipeline receives sequential instructions from memory while prior instructions are implemented in other portions. Pipeline processing can be seen in both the data and instruction streams.
In this article, we will dive deeper into the Instruction Pipeline in Computer Architecture according to the GATE Syllabus for (Computer Science Engineering) CSE. Keep reading ahead to learn more.
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Instruction Pipeline in Computer Architecture
Pipeline processing can happen not only in the data stream but also in the instruction stream. To perform tasks such as fetching, decoding and execution of instructions, most digital computers with complicated instructions would require an instruction pipeline.
In general, each and every instruction must be processed by the computer in the following order:
1. Fetching the instruction from memory
2. Decoding the obtained instruction
3. Calculating the effective address
4. Fetching the operands from the given memory
5. Execution of the instruction
6. Storing the result in a proper place
Each step is carried out in its own segment, and various segments may take different amounts of time to process the incoming data. Furthermore, there are occasions when multiple segments request memory access at the very same time, requiring one segment to wait unless and until the memory access of another is completed.
If the instruction cycle is separated into equal-length segments, the organisation of an instruction pipeline will become much more efficient. A four-segment type of instruction pipeline refers to one of the most common instances of this style of organisation.
A four-segment instruction pipeline unifies two or more distinct segments into a single unit. For example, the decoding of the instruction and the calculation of the effective address can be merged into a single segment.
A four-segment instruction pipeline is illustrated in the block diagram given above. The instructional cycle is divided into four parts:
Segment 1
The implementation of the instruction fetch segment can be done using the FIFO or first-in, first-out buffer.
Segment 2
In the second segment, the memory instruction is decoded, and the effective address is then determined in a separate arithmetic circuit.
Segment 3
In the third segment, some operands would be fetched from memory.
Segment 4
The instructions would finally be executed in the very last segment of a pipeline organisation.
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