17 Nov 2023: PIB Summary for UPSC

TABLE OF CONTENTS

1. Indo-Pacific Economic Framework for Prosperity (IPEF) Supply Chain Agreement
2. RISC-V (DIR-V) Program

1. Indo-Pacific Economic Framework for Prosperity (IPEF) Supply Chain Agreement

Syllabus: GS-2, International Relations

Prelims: Indo-Pacific Economic Framework for Prosperity (IPEF)

Context:

IPEF Supply Chain Agreement signed by the 14 IPEF Partners.

Details:

• The third Indo-Pacific Economic Framework for Prosperity (IPEF) Ministerial Meeting was held in San Francisco, California on 14 November 2023 hosted by the US.
• IPEF was launched jointly by the USA and other partner countries of the Indo-Pacific region on May 23, 2022, in Tokyo.
• The agreement will establish the structures to enable parties to work together on supply chains, including by developing a deeper shared understanding of regional supply chains, improving crisis response capabilities for supply chain disruptions, sharing information and best practices on supply chain opportunities and vulnerabilities, facilitating business matching and investments to strengthen supply chains, promoting supply chain resilience in critical sectors and key goods, and promoting labour rights and workforce development across IPEF supply chains.

Read more on the Indo-Pacific Economic Framework in the linked article.

2. RISC-V (DIR-V) Program

Syllabus: GS-2, Govt Schemes; GS-3, Science & Technology

Prelims: RISC-V (DIR-V) Program

Context:

Union Minister flagged off the Nationwide Roadshow on Digital India RISC-V (DIR-V) Program.

RISC-V (DIR-V) Program:

• The DIR-V program aims to uplift India’s semiconductor ecosystem.
• The program has the objective of promoting indigenous innovation in the field of microprocessors.
• The three key principles of the program are innovation, functionality, and performance.
• India’s computing systems will leverage the DIR-V (Digital India RISC V) program and will have a serious presence in all the capabilities that we need in the automotive, space tech, IoT sensors and mobility.
• RISC-V is an open-source computer model. It is an instruction set architecture developed by the University of California, Berkeley.
  • RISC-V stands for ‘Reduced Instruction Set Computer’ and ‘V’ is for fifth generation.
• The aim is to establish India as a RISC-V Talent Hub for the world and a supplier of RISC-V System on Chips for servers, mobile devices, automotive, IOT and microcontrollers worldwide.

Read the previous PIB articles here.