Question

A 4-bit synchronous counter with a series carry, uses flip-flop and AND gates, having a propagation delay of 30 ns and 10 ns respectively. The maximum time interval required between two successive clock pulses for reliable operation of the counter is

• A. 10 ns
• B. 30 ns
• C. 40 ns
• D. 50 ns

Answer 1

The correct option is D 50 ns

For a 'n' bit synchronous counter with a series carry

$T_{CLK}\ge t_{pdff}+(n-2)\times 10ns$

$T_{CLK}\ge 50ns$

So option (d) is correct.