Question

A PMOS transistor is to be used in sample and hold circuit as shown in figure below. The transistor has ${\mu }_p{C}_{ox}=100\mu A/V^2$ and $V_{TP}=-1V$. The circuit needs to sampled at a clock frequency of 20 MHz with 50% duty cycle. If the sample voltage must settle to atleast 99% of input voltage and if the MOSFET is assumed to be a linear resistor. Then the $\left(\frac{W}{L}\right)$ ratio of PMOS is________.
Assume, C = 5 pF and control gate voltage = 5 V. Initially capacitor is uncharged.

• A. 3.5
• B. 1.5
• C. 2.5
• D. 4.5

Answer 1

The correct option is C 2.5

The MOSFET will operate in active region if it is to act as resistor. So drain current $I_D$ is given as

$I_D=-{\mu }_p{C}_{ox}\left(\frac{W}{L}\right)(V_{GS}-V_{TP}-\frac{1}{2}{V}_{DS})V_{DS}$

For linear characteristics, we assume $|V_{GS}-V_{TP}|>>\frac{V_{DS}}{2}$

$I_D=-{\mu }_p{C}_{ox}\left(\frac{W}{L}\right)(V_{GS}-V_{TP})V_{DS}$

$={\mu }_p{C}_{ox}\left(\frac{W}{L}\right)(V_{SG}+V_{TP})V_{DS}$

Let the resistance between its source and drain is $R_M$

$R_M=\frac{1}{\frac{\partial I_D}{\partial V_{DS}}}=\frac{1}{{\mu }_p{C}_{ox}\left(\frac{W}{L}\right)(V_{SG}+V_{TP})}$

with clock frequency of 20 MHz and duty cycle 50%, sampling time will be $\frac{1}{2\times 20}=25ns$.
For an input voltage $V_i$, with an initially uncharged capacitor, the capacitor voltage $\left(V_C\right)$ will vary,

if the switch is closed at t = 0, as

$V_C\left(t\right)=V_i(1-e^{-t/R_{M}C})$

for $V_L(t=25ns)=0.99V_i=V_i[1-e^{-25ns/R_{M}C}]$

$R_M=\frac{-25ns}{C\times ln\left(0.01\right)}=\frac{-25ns}{5pF\times ln\left(0.01\right)}=1.086k\Omega$

or $\frac{1}{{\mu }_p{C}_{ox}\left(\frac{W}{L}\right)(V_{SG}+V_{TP})}=1.086kW$

$\left(\frac{W}{L}\right)=\frac{1}{\left(\frac{100\mu A}{V^2}\right)(5-1)\left(1.086k\right)}=2.3$