Question

A student has made a $3-$bit binary down counter and connected to the $R-2R$ ladder type $DAC$ [Gain $=(-1K\Omega /2R)$ as shown in figure to generate a staircase waveform. The output achieved is different as shown in figure. What could be the possible cause of this error?

Answer 1

Initial stage of the counter $=(111{)}_2=(7{)}_{10}$
So output wll be equal to $7V$
Next state of counter $=(110{)}_2=(6{)}_{10}$
So output should be $=6V$
But output is $3V$ that means LSB of counter is connected to MSB to DAC and MSB of counter is connected to LSB of DAC.
Similarly next state of counter $=(101{)}_2=(5{)}_{10}$
Input to DAC $=(101{)}_2=(5{)}_{10}$
So output $=5V$
When counter goes to $(100{)}_2$ then input to DAC $=(001{)}_2=(1{)}_{10}$
So output $=1V$
So connections are not proper.