A) Given, input for the circuit, A and B.
Output for the circuit, Y.
Output of the first NAND gate,
X=¯¯¯¯¯¯¯¯¯¯¯A.B
This output X act as input for the next NAND gate,
So, output of the combination,
Y=¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯A.B.¯¯¯¯¯¯¯¯¯¯¯A.B
Y=¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯A.B+¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯A.B
Y=A.B
INPUTSOUTPUTABY000010100111
This is the logic operation for AND gate.
Final answer: AND gate.
B) A is input to the upper NAND gate output of whose goes to the rightmost NAND gate. Also, B is input to the lower NAND gate whose output goes to the rightmost NAND gate.
Output of the first NAND gate,
Y1=¯¯¯¯A
Output of the second NAND gate,
Y2=¯¯¯¯B
So, output of the combination,
Y=¯¯¯¯¯¯¯¯¯¯¯¯¯¯A.¯¯¯¯B
Y=¯¯¯¯¯¯¯¯A+¯¯¯¯¯¯¯¯B
Y=A+B
INPUTSOUTPUTABY000011101111
This is the logic operation for OR gate.
Final answer: OR gate.