Comparing the time T1 taken for a single instruction on a pipelined CPU with time T2 taken on a non-pipelined but identical CPU, we can say that
A
T1 plus T2 is the time taken for one instruction fetch cycle
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B
T1 ≥ T2
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C
T1 < T2
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D
T1 ≤ T2
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Solution
The correct option is B T1 ≥ T2
In pipelined CPU, there will be buffer delay and stage delay. So for 1 instruction nonpipelined CPU takes less time compared to pipelined CPU.