Question
Consider a 2-way set associative cache with 4. blocks. The main memory contains 16 blocks. CPU generates requests for main memory blocks in following order:
0,4, 0, 8, 0, 4,1, 3, 1, 5, 1,3
Consider LRU (Least recently used) block replacement. Let's assume number of conflict misses for above requests is x and number of capacity misses is y. The value of x + 10y is_______.