Question

Consider a system with single level cache. CPU requests for a memory content which causes a cache miss. Assume there are 2 such memory requests 'i' and 'j' which are sequential requests (first request 'i' and then next request is j) and cause cache miss.
Which of the following statements is/are true?

I. If 'i' causes capacity miss, then j's miss cannot be a conflict miss.
II. lf 'i' causes conflict miss, then j's miss cannot be a capacity miss.
III. If 'i' causes conflict miss, then j's miss can be a compulsory miss.
IV. If 'i' causes compulsory miss. then j's miss also can be a compulsory miss.

Answer 1

option (d)

I. If 'i' causes capacity miss, then the cache is full. which means in this case either next request can have a compulsory miss but not a conflict miss.

II. If 'i' causes conflict miss which means cache is not full and the miss occurs due to tag miss-match at one set/block in cache. Hence bringing the missed block for 'i' cannot make cache full, hence next request 'j' cannot cause capacity miss.

III. A compulsory miss can occur any time.

IV. A compulsory miss can occur any time.