Question

Consider an instruction pipeline with five stages without any branch prediction. Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is 1 ns. A program consisting of 12 instruction $I_1,I_2,I_3,.....I_{12}$ is execute in this pipelined processor. Instruction $I_4$ is the only branch instruction and its branch target is $I_9$. If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is

• A. 165
• B. 132
• C. 176
• D. 328

Answer 1

The correct option is A 165

Number of stages = 5

Stage maximum delay = 10 + 1 = 11 ns

$I_4$ instruction $4^{th}$ stage output is a target address.

So, number of instruction in pipeline = 11

$So,E{T}_{pipe}=(K+n-1)t_p$

$=(5+11-1)\times 11ns=165ns$