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Question

Consider the block diagram of a frequency Synthesizer consisting of a phase locked loop (PLL) as shown below:

if the reference input frequency(fin) to the above synthesizer is 0.48MHz and the frequency divider in the feedback path has N=50, then the steady state output frequency (fout)will be....MHz.
  1. 24

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Solution

The correct option is A 24
for the given frequency synthesizer, in the steady state, foutN=fn fout=Nfn=50×0.48=24MHz


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