Question

Consider the circuit shown in the figure below:



If the input voltage $v_{in}\left(t\right)$ is a sinusoidal signal with a maximum value of $V_m$, then the steady state output voltage $V_0$ of the circuit will be equal to (Assume that the diodes are ideal)

Answer 1

(i) For the diode $D_1$ to conduct $v_{in}\left(t\right)>0$ (i.e. $v_{in}\left(t\right)$ for positive half-cycle)


(ii) For the diode $D_2$ to conduct $v_{in}\left(t\right)$ < 0 (i.e. $v_{in}$ for negative half-cycle)



Thus at steady state the output voltage can be represented as,



$\therefore$ $V_0=-2V_m$