Question

Consider the following data path of a CPU



The ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycle are needed for memory read operation - the first one for loading address in the MAR and the next one for loading data form the memory but into the MDR

The instruciton "add R0, R1" has the register transfer interpretation R0 <= R0 + R1. The minimum number of clock cycles needed for execution cycle of this instruction is

• A. $5$
• B. $3$
• C. $2$
• D. $4$

Answer 1

The correct option is B $3$

$RTL{R}_0\Leftarrow R_0+R_1$

The sequence of microinstruction take place in following cycles.

$Icycle:R_{1out},S_{in}$
$IIcycle:R_{2out},T_{in}$
$IIIcycle:S_{out},T_{out},AL{U}_{add},R_{in}$

$\therefore$ 3 cycles will be required to execute.