Question

Figure I shows a 4-bit ripple carry adder realized using full adders and Figure II shows the circuit of a full-adder (FA). The propagation delay of the XOR, AND and OR gates in Figure II are 20 ns, 15 ns and 10 ns, respectively. Assume all the inputs to the 4-bit adder are initially reset to 0.

Figure I:


Figure II:



At t= 0, the inputs to the 4-bit adder are changed to $X_3{X}_2{X}_1{X}_0=1100,Y_3{Y}_2{Y}_1{Y}_0=0100and{Z}_0=1$. The output of the ripple carry adder will be stable at t (in ns) =

Answer 1

In this question inputs to be added are :
$X_3{X}_2{X}_1{X}_0=1100$
$Y_3{Y}_2{Y}_1{Y}_0=0100$ and $Z_0=1$
For this combination of addition, total minimum delay depends on the addition of most-significant two bits (since least significant two bits are zeros they do not cause any change in $Z_{1}and{Z}_2)$. So, in the process of addition of given two digits, waveforms at $Z_{1}and{Z}_2$ become stable at t = 0 itself.


In the above diagram, the waveform at A and B become stable at t = 0 itself, as the applied input combinations do not cause any change. So, for the given combination of inputs, outputs will settle at t = 50 ns.