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Question

For the NMOS logic gate shown in figure, the logic function implemented is









A
(¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯A+B).C+¯D.¯E
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B
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯A.(B+C)+D.E
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C
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ABCDE
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D
(AB+¯C).(¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯D+E
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Solution

The correct option is B ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯A.(B+C)+D.E
F = ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯A.(B+C)+DE

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