(D)
Since block size is unchanged, number of bits in block offset will remain unchanged. As, associativity of cache is doubled, number of lines in one set is doubled, number of sets reduces to half, number of bits in set number decreases by 1 and number of bits in tag increments by 1. All this results in the decrease in the width of set index decoder and increase in the width of tag comparator. As, Associativity and number of lines are doubled then new associativity of cache will be 2K. To handle this new associativity, size of multiplexers must be 2K×1. So, width of way selection multiplier also increases. Only the width of processor to main memory data bus remains unchanged because it depends on the number of bits in block offset which is unchanged here. It has nothing to do with cache associativity.