Question

In 2's complement addition, overflow

• A. cannot occur when a +ve value is added to a -ve value
• B. is flagged whenever there is carry from sign bit addition
• C. is flagged when the carries from sign bit and previous bit match
• D. None of the above

Answer 1

The correct option is A cannot occur when a +ve value is added to a -ve value

When two signed 2's complement numbers are added, overflow is detected if:

1. both operands are positive and the result is negative, or

2. both operands are negative and the result is positive.

Obviously, adding two numbers of opposite sign can't produce overflow because addition of different signed number is equal to subtraction.