Question

In the circuit shown below, the condition to be satisfied such that the silicon transistor will never enter into saturation is (Assume $V_{BE}=0.7V,V_{CE\left(sat\right)}=0V$)

• A. $R_B>116.25k\Omega$
• B. $R_B<116.25k\Omega$
• C. $R_B>232.5k\Omega$
• D. $R_B<232.5k\Omega$

Answer 1

The correct option is C $R_B>232.5k\Omega$

Transistor will enter into saturation region for $V_{CE\left(sat\right)}=0V$
Applying KVL in collector emitter loop,

$-20+(I_C\times 10k)+V_{CE.sat}=0$

$I_C=\frac{20-V_{CE\left(sat\right)}}{10k}=2mA$

$I_B=\frac{I_C}{\beta }=\frac{2\times {10}^{-3}}{50}=40\mu A$

Applying KVL in base emitter loop

$-10+I_B{R}_B+0.7=0$

$R_B=\frac{10-0.7}{40\times {10}^{-6}}=232.5k\Omega$

$\therefore$ For all values of $R_B>232.5k\Omega$ the transistor will not operate in saturation region.