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Question

In the diagram shown below, the input is across the terminals A and C and the output is across B and D Then the output is
1102744_01ea8f7b131f4bffbbc6b073a40cebd0.png

A
Zero
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B
Same as input
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C
Full wave rectified
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D
Half wave rectified
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Solution

The correct option is C Full wave rectified
During half cycle whenVM>VN, D1andD3 are forward biased. The path of current is MABPQDCNM.
In second half cycle,VN>VM, D2andD4 are forward biased while D1andD3 are reverse biased. Hence, path of current is ,NCBPQDAMN.
Therefore, in both half cycles, current flows from PtoQ from load resistance RL. It is full wave rectifier.

1462296_1102744_ans_957d6e1b6ad743f8a7aa50c500bf95ed.png

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