In the digital circuit shown in figure the flip-flops have set time of 5ns and a worst case delay of 15ns. The AND gate has a delay of 5ns. Maximum possible clock rate for the circuit to operate faithfully is
A
21MHz
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B
22MHz
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C
25MHz
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D
30MHz
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Solution
The correct option is C25MHz Initially, two flip-flops have fixed inputs so, no requirement of setup time.
These two flip flops cause a delay of 30ns and then AND cause a delay of 5ns.
Total delay to reach the third flip flop =35ns. Output of AND gate is connected to the inputs of third flip flop