Question

In the digital circuit shown in figure, the flip-flops have set time of $5ns$ and a worst case delay of $15ns$. The AND gate has a delay of $5ns.$ Maximum possible clock rate for the circuit to operate faithfully is

Answer 1

Initially, two flip-flops have fixed inputs so, no requirement of setup time.

These two flip flops cause a delay of $30ns$ and then AND cause a delay of $5ns.$

Total delay to reach the third flip flop $=35ns$. Output of AND gate is connected to the inputs of third flip flop.

Third flip flop causes a setup time$=5ns$

So, $T\ge 40ns$

$f\le \frac{1}{40\times {10}^{-9}}$

$f\le 25\text{MHz}$

$\therefore f_{\text{max}}=25\text{MHz}$