Question

The circuit shown consists of J-K flip-flops, each with an active low asynchronous reset (${\overline{R}}_d$ input).
the counter corresponding to this circuit is

• A. a modulo-5 binary up counter
• B. a modulo-6 binary down counter
• C. a modulo-5 binary down counter
• D. a modulo-6 binary up counter

Answer 1

The correct option is A a modulo-5 binary up counter

Q is applied as negative edge triggering clock.
$\Rightarrow$ Counter is up counter.
Reset signal = $\overline{Q_2.Q_0}$
The counter resets at 101
$\Rightarrow$ Counter is MOD-5