The diagram of a logic gate circuit is given below. The output Y of the circuit is represented by
A
A⋅(B+C)
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B
A⋅(B⋅C)
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C
A+(B⋅C)
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D
A+(B+C)
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Solution
The correct option is CA+(B⋅C) Output of upper OR gate =A+B Output of lower OR gate =A+C Net output Y=(A+B)(A+C) =AA+AC+BA+BC =A(1+C)+BA+BC[∵AA=A] =A+BA+BC[∵1+C=1] =A(1+B)+BC[∵1+B=1] =A+BC=A+(B⋅C).