MyQuestionIcon

1

You visited us 1 times! Enjoying our articles? Unlock Full Access!

The digital b...

Question

The digital block in the figure is realized using two positive edge triggered D-flip-flops. Assume that for t < $t_{0}$ , $Q_{1}$ = $Q_{2}$ = 0. The circuit in the digital block is given by:

Open in App

Solution

It is given that clock is positive edge triggered then only option (a) and (c) are possible. Out of which only (c) option gives the required result.

Suggest Corrections

thumbs-up

0

Similar questions

Q. For each of the positive edge-triggered J-K flip-flop used in the following figure, the propagation delay is

Δ

Which of the following waveforms correctly represents the output at

Q_{1}

?

Q. The outputs of the two flip-flops

Q_{1}

Q_{2}

in the figure shown are initialized to 0, 0. The sequence generated at

Q_{1}

upon application of clock signal is

Q. The frequency of the clock signal applied to the rising edge triggered

D

flip-flop shown in figure is

10 k H z

. The frequency of the signal available at

Q

Q. In the digital circuit shown in figure, the flip-flops have set time of

5 n s

and a worst case delay of

15 n s

. The AND gate has a delay of

5 n s .

Maximum possible clock rate for the circuit to operate faithfully is

Q. Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor R = 10 k

Ω

and the supply voltage is 5 V. The D flip-flops

D_{1}

D_{2}

D_{3}

D_{4}

D_{5}

are initialized with logic values 0,1,0,1 and 0, respectively. The clock has a 30% duty cycle.

The average power dissipated (in mW) in the resitor R is ___

View More

Join BYJU'S Learning Program

similar_icon

Related Videos

lock

Pictographs and Bar Graphs

Watch in App

Join BYJU'S Learning Program

CrossIcon