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B
NOR gate with output O=¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯X+Y
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C
NAND gate with output O=¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯X−Y
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D
NOR gate with output O=¯¯¯¯¯X.¯¯¯¯Y
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Solution
The correct option is A NOR gate with output O=¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯X+Y The given logic circuit is the combination of OR and NOT gates. So it should be the NOR gate. Besides, the NAND gate is the combination of AND and NOT gates.
The output of NOR gate will be O=¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯X+Y and output of the NAND gate will be O=¯¯¯¯¯¯¯¯¯XY=¯¯¯¯¯X+¯¯¯¯Y (by de Morgan's law)