The logic gate realized from the circuit as shown in figure is ( and are inputs and is output)
XOR
Explanation for correct option:
In case of option B,
P | Q | Y |
0 | 0 | 0 |
0 | 1 | 1 |
1 | 0 | 1 |
1 | 1 | 0 |
Explanation for incorrect option:
In case of option A,
P | Q | Y |
0 | 0 | 1 |
0 | 1 | 0 |
1 | 0 | 0 |
1 | 1 | 1 |
In case of option C,
P | Q | Y |
0 | 0 | 1 |
0 | 1 | 0 |
1 | 0 | 0 |
1 | 1 | 0 |
In case of option D,
P | Q | Y |
0 | 0 | 0 |
0 | 1 | 1 |
1 | 0 | 1 |
1 | 1 | 1 |
Hence, option B is correct.