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Question

The output Y of the gate shown in the figure will be represented by :


A
Y=AB
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B
Y=A+B
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C
Y=¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯A+B
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D
Y=A¯¯¯¯B+B¯¯¯¯A
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Solution

The correct option is B Y=A+B
Let the output from the 1st gate and the 2nd gate be Y1 and Y2

Y1=¯¯¯¯¯¯¯¯¯¯¯¯AA=¯¯¯¯A

Similarly, Y2=¯¯¯¯¯¯¯¯¯¯¯¯BB=¯¯¯¯B

Now the inputs to the final NAND gate is Y1 and Y2.

Y=¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯Y1Y2

Y=¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯A¯¯¯¯B

By DeMorgan's theorem,

Y=¯¯¯¯¯¯¯¯A+¯¯¯¯¯¯¯¯B

Y=A+B

Hence, option (B) is correct.

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