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Question
A nonpipelined single cycle processor operating at 100 MHz is converted into a synchronous pipelined processor with five stages requiring 2.5 nsec, 1.5 nsec, 2 nsec, 1.5 nsec and 2.5 nsec respectively. The delay of the latches is 0.5 nsec. The speedup of the pipelined processor for a large number of instructions is
A nonpipelined single cycle processor operating at 100 MHz is converted into a synchronous pipelined processor with five stages requiring 2.5 nsec, 1.5 nsec, 2 nsec, 1.5 nsec and 2.5 nsec respectively. The delay of the latches is 0.5 nsec. The speedup of the pipelined processor for a large number of instructions is
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Solution
The correct option is B 3.33
Time needed for non-pipelined process (NP)
= Sum of time for each state
= (2.5 + 1.5 + 2 + 1.5 + 2.5) nsec
= 10 nsec
Time needed for pipelined processor
(P)=TP+Buffer delay
TP = max (all stages time)
= max (2.5, 1.5, 2, 1.5, 2.5) nsec
= 2.5 nsec
P=TP+Buffer delay
= 2.5 nsec + 0.5 nsec
= 3 nsec
Speedup=Nonpipelinetimepipelinetime
=10nsec3nsec
=3.33
Time needed for non-pipelined process (NP)
= Sum of time for each state
= (2.5 + 1.5 + 2 + 1.5 + 2.5) nsec
= 10 nsec
Time needed for pipelined processor
(P)=TP+Buffer delay
TP = max (all stages time)
= max (2.5, 1.5, 2, 1.5, 2.5) nsec
= 2.5 nsec
P=TP+Buffer delay
= 2.5 nsec + 0.5 nsec
= 3 nsec
Speedup=Nonpipelinetimepipelinetime
=10nsec3nsec
=3.33
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