Question

Consider a pipelined processor with the following four stages

IF: Instruction Fetch

ID: Instruction Decode and Operand Fetch

EX: Execute

WB: Write Back

The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock cycle for the EX stage depends on the instruction. The ADD and SUB instructions need 1 clock cycle and the MUL instructions need 3 clock cycles in the EX stage. Operands forwarding is used in the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions?

ADD	R2,	R1,	R0	R2 $\leftarrow$ R1 + R0
MUL	R4,	R3,	R2	R4 $\leftarrow$ R3 * R2
SUB	R6,	R5,	R4	R6 $\leftarrow$ R5 - R4

• A. 14
• B. 10
• C. 7
• D. 8

Answer 1

The correct option is D 8

Pipelined processor has 4 stages IF, ID, EX, WB

Clock Cycles Instruction

1 ADD

1 SUB

3 MUL

Consider the following diagram



So total required clocks cycle is 8.