A processor user 2-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical adresses are both 32 bits wide. The memory is byte addressable. For virtual to physical address translation, the 10 most significant bits of the virtual address are used as index into the first level page table while the next 10 bits are used as index into the second level page table. The 12 least significant bits of the virtual address are used as offset within the page. Assume that the page table entries in both levels of page tables are 4 bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of 96% . The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit ratio of 90 %. Main memory access time is 10 ns, cache access time is 1 ns. and TLB access time is also 1 ns.
Suppose a process has only the following pages in its virtual address space: two contiguous code pages starting at virtual address 0 x 00000000, two contiuous data page starting at virtual address 0 x FFFFF000. The amount of memory required for storing the page tables of this process is
A processor user 2-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical adresses are both 32 bits wide. The memory is byte addressable. For virtual to physical address translation, the 10 most significant bits of the virtual address are used as index into the first level page table while the next 10 bits are used as index into the second level page table. The 12 least significant bits of the virtual address are used as offset within the page. Assume that the page table entries in both levels of page tables are 4 bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of 96% . The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit ratio of 90 %. Main memory access time is 10 ns, cache access time is 1 ns. and TLB access time is also 1 ns.
Suppose a process has only the following pages in its virtual address space: two contiguous code pages starting at virtual address 0 x 00000000, two contiuous data page starting at virtual address 0 x FFFFF000. The amount of memory required for storing the page tables of this process is
The correct option is C 16KB
Logical address = 32 bits
P1
P2
P3
10 bits 10 bits 12 bits
P1= 1st level page table.
P2= 2nd level page table.
d = Page offset
First virtual address given
Address will be found in first level page table first block.
Second virtual address given
Address will be found in first level page table second block.
Third virtual address given
Address will be found in first level page table last block.
To execute the process we need to bring all the above 4 page tables in main memory.
4×210×4 B=16 KB
Logical address = 32 bits
| P1 | P2 | P3 |
P1= 1st level page table.
P2= 2nd level page table.
d = Page offset
First virtual address given
Address will be found in first level page table first block.
Second virtual address given
Address will be found in first level page table second block.Third virtual address given
Address will be found in first level page table last block.To execute the process we need to bring all the above 4 page tables in main memory.4×210×4 B=16 KB
