Consider a three word machine instruction

$A D D A [R_{0}], @ B$

The first operand (destination) " $A [R_{0}]$ " uses indexed addressing mode with $R_{0}$ as the index register. The second operand (source) "@B" uses indirect addressing mode. A and B are memory addresses residing at the second and the third words, respectively. The first word of the instruction specifies the opcode, the index register designation and the source and destination addressing modes. During execution of ADD instruction, the two operands are added and stored in the destination (first operand).

The number of memory cycles needed during the execution cycle of the instruction is

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Solution

The correct option is A 6
$A D D A [R_{0}], @ B$

$A [R_{0}]$ uses indexed addressing mode as follow such that $R_{0}$ as the index register

$R e g s [R 3] \leftarrow R e g s [R 3] + M e m [R e g s [B] + R e g s [R 0]] . . . (i)$

And @B uses indirect as follows

$A D D A [R_{0}], @ B$

$R e g s [R_{0}]$ $\leftarrow$ $R e g s [R_{0}] + M e m [M e m [B]] . . . (i i)$

So the first instruction needed 3 memory cycles and the second needed 2 and one memory cycle is needed for writing the result into the memory.

So total 6 memory cycles are needed to execute

$A D D A [R_{0}], @ B$

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