Question

For a pipelined CPU with a single ALU, consider the following situations

1. The $j+1^{st}$ instruction uses the result of the $j^{th}$ instruction as an operand

2. The execution of a conditional jump instruction

3. The $j^{th}$ and $j+1^{st}$ instructions require the ALU at the same time

Which of the above can cause a hazard?

• A. 1 and 2 only
• B. All the three
• C. 3 only
• D. 2 and 3 only

Answer 1

The correct option is B All the three

(i) The $j+1^{st}$ instruction uses the result of the $j^{th}$ instruction as an operand then read-after-write (RAW) hazard occurs. It is a part of data dependency.

(ii) The execution of a conditional jump instruction causes a flushing so conditional dependency occurs.

(iii) The $j^{th}$ and $j+1^{st}$ instructions require the ALU at the same time causes write-after-read (WAR) hazard.