The so called classic common emitter configuration uses a potential divider network to bias the transistors Base. Power supply Vcc and the biasing resistors set the transistor operating point to conduct in the forward active mode. With no signal current flow into the Base, no Collector current flows, (transistor in cut-off) and the voltage on the Collector is the same as the supply voltage, Vcc. A signal current into the Base causes a current to flow in the Collector resistor, Rc generating a voltage drop across it which causes the Collector voltage to drop.

Then the direction of change of the Collector voltage is opposite to the direction of change on the Base, in other words, the polarity is reversed. Thus the common emitter configuration produces a large voltage amplification and a well defined DC voltage level by taking the output voltage from across the collector as shown with resistor R_Lrepresenting the load across the output.

Please explain me the above paragraphs.
And also conclude that how is the input impedance of common emitter configuration high and how does this affect the high current gain and power gain of this type of configuration.

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In a common emitter configuration of a transistor, the voltage drop across a 500Ω resistor in the collector circuit is 0.5 V when the collector supply voltage is 5V. If the current gain in the common base mode is 0.96, the base current is :

The correct option is D 124 mAlc=0.5500=1mAα=0.96Relationbetweenαandβis1α−1βis⇒1β=1α−11β=10.96−1β=24⇒β=lClB=24orlB=lCβ=124mA

In a common emitter configuration of a transistor, the voltage drop across a 500 $Ω$ resistor in the collector circuit is 0.5 V when the collector supply voltage is 5V. If the current gain in the common base mode is 0.96, the base current is :