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Cache Address Mapping: Set Associative Mapping 1

The main memo...

Question

The main memory of a computer has 'P' number of blocks and cache memory has 'Q' number of block and it is designed with 4 way block set associative mapping techinque. Number of bits in tag field of its physical address format is

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Solution

option (c)

In set associative mapping Tag field size
$= l o g_{2} \frac{M}{S},$
where M = number of blocks in main memory
S = number of sets in cache memory.
$h e r e S = \frac{Q}{4}$
$Hence, tag field size l o g_{2}, \frac{P}{Q / 4} = l o g_{2} \frac{4 P}{Q}$

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