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Standard XII
Business Studies
Importance of Planning
The performan...
Question
The performance of a pipelined processor suffers if
A
the pipeline stages have different delays
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B
the pipeline stages share hardware resources
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C
consecutive instructions are dependent on each other
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D
All of the above
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Solution
The correct option is
D
All of the above
Hazards are caused due to dependencies.
Different dependencies in pipelined processor are:
1. Structural dependency : The pipeline stages have different delays.
2. Control dependency : Consecutive instructions are dependent as each other.
3. Data dependency : The pipeline stages share hardware resources.
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Consider a pipelined processor with the following four stages
IF: Instruction Fetch
ID: Instruction Decode and Operand Fetch
EX: Execute
WB: Write Back
The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock cycle for the EX stage depends on the instruction. The ADD and SUB instructions need 1 clock cycle and the MUL instructions need 3 clock cycles in the EX stage. Operands forwarding is used in the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions?
ADD
R2,
R1,
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R2
←
R1 + R0
MUL
R4,
R3,
R2
R4
←
R3 * R2
SUB
R6,
R5,
R4
R6
←
R5 - R4
Q.
Consider a 4 stage pipeline processor. The number of cycles needed by the four instructions I1, I2, I3, I4 in stages S1, S2, S3, S4 is shown below:
S1
S2
S3
S4
I1
2
1
1
1
I2
1
3
2
2
I3
2
1
1
3
I4
1
2
2
2
What is the number of cycles needed to execute the following loop?
for (i = 1 to 2) {I1; I2; I3; I4;}
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