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Standard XII
Business Studies
Importance of Organising
The total siz...
Question
The total size of address space in a virtual memory system is limited by
A
the length of
M
A
R
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B
All of the above
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C
the available main memory
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D
the available secondary storage
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Solution
The correct option is
D
the available secondary storage
Since virtual memory is implemented on secondary storage.
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Similar questions
Q.
The size of the minimum address bus which can be used to access a memory of size
1024
×
8
bit is ______
Q.
Consider the following declaration of a two-dimensional array in C
char a[100][100];
Assuming that the main memory is byte-addressable and that the array is stored starting form memory address 0, the address of a[40][50] is
Q.
Consider the following program segment for a hypothetical CPU having three user registers R1, R2 and R3.
Instruction Operation Instruction
Size
(in words)
MOV R1, 5000 ; R1
←
Memory [5000] 2
MOV R2, (R1) ; R2
←
Memory [(R1)] 1
ADD R2, R3 ; R2
←
R2 + R3 1
MOV 6000, R2 ; Memory [6000]
←
R2 2
HALT ; Machine halts 1
Consider that the memory is word addressable with size 32 bits and the program has been loaded starting from memory location 1000 (decimal). If an interrupt occurs during the ADD instruction, what will be the return address pushed on to the stack.
Q.
Consider the following program segment for a hypothetical CPU having three user registers R1, R2 and R3.
Instruction Operation Instruction
Size
(in words)
MOV R1, 5000 ; R1
←
Memory [5000] 2
MOV R2, (R1) ; R2
←
Memory [(R1)] 1
ADD R2, R3 ; R2
←
R2 + R3 1
MOV 6000, R2 ; Memory [6000]
←
R2 2
HALT ; Machine halts 1
Consider that the memory is byte addressable with size 32 bits, and the program has been loaded starting from memory location 1000 (decimal). If an interrupt occurs while the CPU has been halted after executing the HALT instruction, the return address (in decimal) saved in the stack will be
Q.
Consider a hypothetical processor with a instruction of type LW R1, 20(R2), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R1. The effective address of the memory location is obtained by the addition of a constant 20 and the contents of register R2. Which of the following best reflects the addressing mode implemented by this instruction for the operand in memory?
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