The truth table for system of four NAND gates as shown in the figure is

$\begin{matrix} A & B & Y 0 & 0 & 0 0 & 1 & 0 1 & 0 & 1 1 & 1 & 1 \end{matrix}$

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$\begin{matrix} A & B & Y 0 & 0 & 1 0 & 1 & 1 1 & 0 & 0 1 & 1 & 0 \end{matrix}$

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$\begin{matrix} A & B & Y 0 & 0 & 1 0 & 1 & 0 1 & 0 & 0 1 & 1 & 1 \end{matrix}$

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$\begin{matrix} A & B & Y 0 & 0 & 0 0 & 1 & 1 1 & 0 & 1 1 & 1 & 0 \end{matrix}$

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Solution

The correct option is D
$\begin{matrix} A & B & Y 0 & 0 & 0 0 & 1 & 1 1 & 0 & 1 1 & 1 & 0 \end{matrix}$

Outputs of the gates are marked as $y$ , $y_{1}$ and $y_{2}$ :

A NAND gate gives low output when both the inputs are high, otherwise, it gives a high output. Now, the truth table is

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The truth table for system of four NAND gates as shown in the figure is

The correct option is D ABY000011101110 Outputs of the gates are marked as y, y1 and y2: A NAND gate gives low output when both the inputs are high, otherwise, it gives a high output. Now, the truth table is

The correct option is D
$\begin{matrix} A & B & Y 0 & 0 & 0 0 & 1 & 1 1 & 0 & 1 1 & 1 & 0 \end{matrix}$

Outputs of the gates are marked as $y$ , $y_{1}$ and $y_{2}$ :

A NAND gate gives low output when both the inputs are high, otherwise, it gives a high output. Now, the truth table is