Question

Conisder the following :

No. of cycles to send address to memory = 2
No. of cycles to access main memory = 15
No. of cycles to transfer a data = 2

Assume that main memory is byte addressable and cache block size is 4 bytes. Further assume that clock rate of CPU is 2GHz. The miss penalty time is __________ns.

• A. 40
• B. 50
• C. 30
• D. 35

Answer 1

The correct option is D 35

option (b)

Miss penatly = 2 +(4 * 15) + (4 * 2) = 70 cycles

$\text{Only one time address si sent}\Rightarrow 2cycles$

$\text{4 times (for 4 bytes) memory is accessed}\to 4{}^{\ast }15cycles$

$\text{4 times (for 4 bytes) data is transferred}\Rightarrow 4{}^{\ast }2cycles$

$1cycletime=\frac{1}{2Ghz}=0.5ns$

total time = 70 * 0.5 = 35 ns