Let the clock cycles required for various operations be as follows:
Register to/from memory transfer:
3 clock cycles
ADD with both operands in register:
1 clock cycle
Instruction fetch and decode:
2 clock cycles per word
The total number of clock cycles required to execute the program is
Operation | Instruction Size | (IF + ID) | (OF + PD + WB) |
R0, Memory [5000] | 2 | 2 × 2 C | 3C |
R2 ← Memory [(R1)] | 1 | 1 × 2 C | 3 C |
R2 ← (R2 + R3)] | 1 | 1 × 2 C | 1 C |
Memory [6000] ← R2 | 2 | 2 × 2 C | 3 C |
Machine Halt | 1 | 1 × 2 C | 0 C |
14 C | 10 C |