Digital Logic GATE Questions

A highly popular method used to prepare for the GATE Exam is to practise all the previous years’ GATE Questions to gain perfection. Candidates can practise, analyse and understand concepts while solving them. It will also help you strengthen your time management skills. We have attempted to compile, here in this article, a collection of GATE Questions on Digital Logic.

Candidates are urged to practise these Digital Logic GATE previous years’ questions to get the best results. Digital Logic is an important topic in the GATE CSE question paper, and solving these questions will help the candidates to prepare more proficiently for the GATE exams. Therefore, candidates can find the GATE Questions for Digital Logic in this article to solve and practise before the exams. They can also refer to these GATE previous year question papers and start preparing for the exams.

GATE Questions on Digital Logic

1. Consider Z = X – Y, where X, Y and Z are all in sign-magnitude form. X and Y are each represented in n bits. To avoid overflow, the representation of Z would require a minimum of __________.

(GATE CSE 2019)

1. n + 1 bits
2. n – 1 bits
3. n + 2 bits
4. n bits

Answer (a)

2. In 16-bit 2’s complement representation, the decimal number -28 is __________.

(GATE CSE 2019)

1. 1000 0000 1110 0100
2. 0000 0000 1110 0100
3. 1111 1111 1110 0100
4. 1111 1111 0001 1100

Answer (c)

3. Consider an eight-bit ripple-carry adder for computing the sum of A and B, where A and B are integers represented in 2′s complement form. If the decimal value of A is one, the decimal value of B that leads to the longest latency for the sum to stabilise is ________.

(GATE CSE 2016 Set 2)

1. 0
2. 1
3. Both (a) and (b)
4. Neither (a) nor (b)

Answer (b)

4. The 16-bit 2′s complement representation of an integer is 1111 1111 1111 0101; its decimal representation is __________.

(GATE CSE 2016 Set 1)

1. 10
2. 11
3. 15
4. 20

Answer (b)

5. The smallest integer that can be represented by an 8-bit number in 2′s complement form is ___________.

(GATE CSE 2013)

1. -256
2. -128
3. -127
4. 0

Answer (b)

6. We want to design a synchronous counter that counts the sequence 0−1−0−2−0−3 and then repeat. The minimum number of J−K flip-flops required to implement this counter is ________.

(GATE CSE 2016 Set 1)

1. Between 3 and 4
2. Between 0 and 1
3. Between 4 and 7
4. Between 1 and 2

Answer (a)

7. The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0,0,1,1,2,2,3,3,0,0,…) is _________.

(GATE CSE 2015 Set 2)

1. 1
2. 2
3. 4
4. 3

Answer (d)

8. Consider a 4-bit Johnson counter with an initial value of 0000. The counting sequence of this counter is _______.

(GATE CSE 2015 Set 1)

1. 0, 1, 3, 7, 15, 14, 12, 8, 0
2. 0, 1, 3, 5, 7, 9, 11, 13, 15, 0
3. 0, 2, 4, 6, 8, 10, 12, 14, 0
4. 0, 8, 12, 14, 15, 7, 3, 1, 0

Answer (d)

9. Consider the following representation of a number in IEEE 754 single-precision floating-point format with a bias of 127.

S: 1 E: 10000001 F: 11110000000000000000000

Here S, E and F denote the sign, exponent and fraction components of the floating-point representation.

The decimal value corresponding to the above representation (rounded to 2 decimal places) is ________.

(GATE CSE 2021 Set 1)

1. -7.75
2. 7.75
3. -0.775
4. 0.775

Answer (a)

10. Let the representation of a number in base 3 be 210. What is the hexadecimal representation of the number?

(GATE CSE 2021 Set 1)

1. 21
2. 528
3. 12
4. 15

Answer (d)

11. Let A=1111 1010 and B=0000 1010 be two 8-bit 2′s complement numbers. This product in 2′s complement is ___________.

(GATE CSE 2004)

1. 1100 0100
2. 1001 1100
3. 1010 0101
4. 1101 0101

Answer (a)

12. Zero has two representations in ___________.

(GATE CSE 1999)

1. Sign magnitude
2. 1’s complement
3. Both (a) and (b)
4. None of the above

Answer (c)

13. A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flip-flop as follows. The Q output of the D flip-flop is connected to both the J and K inputs of the JK flip-flop, while the Q output of the JK flip-flop is connected to the input of the D flip-flop. Initially, the output of the D flip-flop is set to logic one, and the output of the JK flip-flop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the Q output of the JK flip-flop when the flip-flops are connected to a free-running common clock? Assume that J = K = 1 is the toggle mode and J = K = 0 is the state-holding mode of the JK flip-flop. Both the flip-flops have non-zero propagation delays.

(GATE CSE 2015 Set 1)

1. 0110110…
2. 0100100…
3. 011101110…
4. 011001100…

Answer (a)

14. Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean function of n variables. What is the minimum size of the multiplexer needed?

(GATE CSE 2007)

1. 2ⁿ line to 1 line
2. 2ⁿ⁺¹ line to 1 line
3. 2^n-1 line to 1 line
4. 2^n-2 line to 1 line

Answer (c)

15. Let f(w,x,y,z)=∑(0,4,5,7,8,9,13,15). Which of the following expressions are NOT equivalent to f?

(P) x′y′z′+w′xy′+wy′z+xz

(Q) w′y′z′+wx′y′+xz

(R) w′y′z′+wx′y′+xyz+xy′z

(S) x’y’z’ + wx’y’ + w’y

(GATE CSE 2007)

1. P only
2. Q and S
3. R and S
4. S only

Answer (b)